Search - dds fpga

[VHDL-FPGA-Verilog] dds

Description: dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
Platform: | Size: 1086464 | Author: liulei | Hits:

[VHDL-FPGA-Verilog] FPGA-basedhigh-performance32-bitfloating-pointnucl

Description: 基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga
Platform: | Size: 7507968 | Author: bonjour | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度，由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:

[Special Effects] VIDEO-FPGA

Description: 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
Platform: | Size: 6034432 | Author: 王刚 | Hits:

[Software Engineering] FPGA

Description: 为了满足科研与实验需要,提出并实现了一种以FPGA和高速D/A为核心,其结构简单,控制灵活,信号质量高的多功能信号源生成系统。该信号源生成系统能够实时产生中心频率在30~130 MHz的各种雷达、通信、导航和白噪声等信号,且产生的各种信号频率、幅度、相位和其他参数均可控。信号源作为基带信号单元配以混频模块,可实现在任意频段的信号。另外,该信号源还可以作为一个通用平台,通过FPGA内部程序的更新来实现其他复杂信号。-This paper presents and makes a multi-functional signal source based on FPGA and high speed D/A which has simple configuration,flexible controlling,and top-quality signals to satisfy needs of the scientific research and experiment.This signal source can generate several signals as radar signals,communication signals,navigation signals,noise signals and so on.These signals have center frequency between 30~130 MHz,its frequency,power,phase and other parameters are adjustable.This signal source can also ...
Platform: | Size: 330752 | Author: 将建 | Hits:

[SCM] ddsdds

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号 (2009-01-04, VHDL, 99KB, 9次) -hgfhtht rrgtsrt rthg rgrswt sgethwrathwtHY TSRTTHSRHGWth rtyhthgrg rgsrg thrsrgsg rgsgrgthsrg
Platform: | Size: 568320 | Author: nbonwenli | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于DDS原理的几种信号发生器的设计的几篇论文，使用FPGA平台或者FPGA和PC共同平台实现-DDS-based signal generator several principles of design, the use of FPGA or FPGA platform and a common platform PC
Platform: | Size: 591872 | Author: 王霄洲 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 如何利用FPGA产生DDS调频信号很具体的-How to make use of DDS generated FM signal FPGA specific
Platform: | Size: 756736 | Author: 梁梁 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于fpga的函数发生器设计通过fpga实现正弦波输出-基于fpga的函数发生器
Platform: | Size: 62464 | Author: 江孝栋 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds 驱动 ad9851 fpga vhdl-ad9851 dds ad9851 fpga vhdl
Platform: | Size: 1544192 | Author: ZHANGLONG | Hits:

[SCM] DDS

Description: 基于FPGA的DDS程序，可产生任意频率任意相位的波形-FPGA-based DDS program, can generate any frequency arbitrary waveform phase
Platform: | Size: 2971648 | Author: juan | Hits:

[VHDL-FPGA-Verilog] DDSVerilog

Description: DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
Platform: | Size: 71680 | Author: caixiang | Hits:

[VHDL-FPGA-Verilog] DDSsinROMsample

Description: fpga DDS ROM数据正弦波形正半周采样程序-fpga DDS ROM sinusoidal waveform is a half weeks of data sampling procedures
Platform: | Size: 747520 | Author: caixiang | Hits:

[SCM] dds

Description: 基于单片机与FPGA的DDS程序代码，产生任意波形-DDS-based MCU with FPGA-code, resulting in arbitrary waveform
Platform: | Size: 345088 | Author: jiangjun | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.
Platform: | Size: 484352 | Author: 蔡野锋 | Hits:

[VHDL-FPGA-Verilog] 51-DDS

Description: 不仅包含FPGA源码还包含51单片机控制源码，已经实现DDS功能，绝对原创。-Includes not only the FPGA source code also includes a 51 SCM control source, has been achieved DDS functions, absolutely original.
Platform: | Size: 2185216 | Author: 张文琪 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的直接数字频率合成器（DDS）的设计-FPGA-based direct digital frequency synthesizer (DDS) design of
Platform: | Size: 1024 | Author: sunshine | Hits:

[Other] DDS

Description: 这个一个基于FPGA的DDS原代码可以生成正弦和余弦两种波形-This is a DDS code bepend on FPGA ,it can generate two waves.
Platform: | Size: 9216 | Author: wuyanjun | Hits:

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[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGA-basedhigh-performance32-bitfloating-pointnucl

[VHDL-FPGA-Verilog] DDS

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

[Special Effects] VIDEO-FPGA

[Software Engineering] FPGA

[SCM] ddsdds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[SCM] DDS

[VHDL-FPGA-Verilog] DDSVerilog

[VHDL-FPGA-Verilog] DDSsinROMsample

[SCM] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] 51-DDS

[VHDL-FPGA-Verilog] dds

[Other] DDS

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